Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common and important semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103, typically a polysilicon line, acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily doped source/drain regions 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). As used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain. As illustrated in FIG. 1, the source/drain regions 105 of a typical MOS transistor are symmetrical. Whether a region acts as a source or drain thus depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.).
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO.sub.2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
The source/drain regions 105, illustrated in FIG. 1, are lightly-doped-drain (LDD) structures. Each LDD structure includes a lightly-doped, lower conductivity region 106 near the channel region 107 and a heavily-doped, higher conductivity region 104 typically connected to the source/drain terminal. Typically, the LDD structures are formed by: implanting, using the gate electrode 103 for alignment, a first dopant into active regions adjacent the gate electrode at relatively low concentration levels to form the lightly-doped regions 106; forming spacers 108 on the gate electrode; and implanting, using the spacers 108 for alignment, a second dopant into the active regions at higher concentration levels to form the heavily-doped regions 104. The substrate is then annealed to drive the dopant in the heavily-doped regions deeper into the substrate 101.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region 107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
Large numbers of such semiconductor devices are used as basic building blocks for most modem electronic devices. In order to increase the capability and performance of electronic devices implemented using semiconductor devices, it is desirable to increase the number of semiconductor devices which may be formed on a given surface area of a chip wafer. It is also desirable to increase the operating speed, reliability and performance of the semiconductor devices. To accomplish these goals, it is desirable to reduce the size of the semiconductor devices without degrading their performance. It is also desirable to increase operating performance and speed of the devices. New semiconductor fabrication processes and devices are therefore needed to continue the trend of reduced semiconductor device size and increased performance.